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HCF4027B
DUAL J-K MASTER SLAVE FLIP-FLOP
s s
s
s
s
s s
s s
SET RESET CAPABILITY STATIC FLIP-FLOP OPERATION - RETAINS STATE INDEFINETELY WITH CLOCK LEVEL EITHER "HIGH" OR "LOW" MEDIUM-SPEED OPERATION - 16MHz (Typ. clock toggle rate at 10V) QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES"
DIP
SOP
ORDER CODES
PACKAGE DIP SOP TUBE HCF4027BEY HCF4027BM1 T&R HCF4027M013TR
DESCRIPTION HCF4027B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4027B is a single monolithic chip integrated circuit containing two identical complementary-symmetry J-K master-slave flip-flops. Each flip-flop has provisions for individual J, K, Set, Reset, and Clock input
signals. Buffered Q and Q signals are provided as outputs. This input-output arrangement provides for compatible operation with the HCF4013B dual D type flip-flop. This device is useful in performing control, register, and toggle functions. Logic levels present at the J and K inputs, along with internal self-steering, control the state of each flip-flop; changes in the flip-flop state are synchronous with the positive-going transition of the clock pulse. Set and Reset functions are independent of the clock and are initiated when a high level signal is present at either the Set or Reset input.
PIN CONNECTION
September 2002
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HCF4027B
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 6, 5 10,11 13, 3 12, 4 9, 7 1, 2 15, 14 8 16 SYMBOL J2, K2 J1, K1 CLOCK1, CLOCK2 RESET1, RESET2 SET1, SET2 Q2, Q2 Q1, Q1 VSS VDD NAME AND FUNCTION Inputs inputs Clock Inputs Reset Inputs Set Inputs Outputs Outputs Negative Supply Voltage Positive Supply Voltage
FUNCTIONAL DIAGRAM
TRUTH TABLE
PRESENT STATE Inputs J H X L X X X X X
X : Don"t Care * : Level Change
NEXT STATE Output CLOCK* Q H H L L Q L L H H NO CHANGE X X X H L H L H H Outputs
K X L X H X X X X
S L L L L L H L H
R L L L L L L H H
Q L H L H X X X X
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HCF4027B
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage.
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V C
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HCF4027B
DC SPECIFICATIONS
Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (A) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 18 TA = 25C Min. Typ. 0.02 0.02 0.02 0.04 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 10-5 5 -1.15 -0.36 -0.9 -2.4 0.36 0.9 2.4 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 0.36 0.9 2.4 Max. 1 2 4 20 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 Value -40 to 85C Min. Max. 30 60 120 600 4.95 9.95 14.95 0.05 0.05 0.05 -55 to 125C Min. Max. 30 60 120 600 Unit
IL
Quiescent Current
A
VOH
High Level Output Voltage Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Output Drive Current
VOL
VIH
VIL
IOH
IOL
Output Sink Current Input Leakage Current Input Capacitance
0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/18
<1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1
V
V
V
V
mA
mA
II
Any Input Any Input
0.1
7.5
1
1
A
pF
CI
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V
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HCF4027B
DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25C, CL = 50pF, RL = 200K, tr = tf = 20 ns)
Test Condition Symbol Parameter VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Min. Value (*) Typ. 150 65 45 150 65 45 200 85 60 100 50 40 70 30 20 90 40 25 Max. 300 130 90 300 130 90 400 170 120 200 100 80 ns Unit
tPLH tPHL Propagation Delay Time(Clock to Q or Q Outputs) tPLH Propagation Delay Time (Set to Q or Reset to Q) Propagation Delay Time (Set to Q or Reset to Q)
ns
tPHL
ns
tTLH tTHL Transition Time
ns
tW
Pulse Width (Clock)
tW
Pulse Width (Set or Reset)
140 60 40 180 80 50
ns
ns 15 4 1
tr, tf
Clock input Rise or Fall Time Setup Time (DATA)
s
tsetup
fMAX
Maximum Clock Input Frequency (1) (toggle mode)
200 75 50 3.5 8 12
100 35 25 7 16 24
ns
MHz
(*) Typical temperature coefficient for all VDD value is 0.3 %/C. (1) Input tr, tf = 5ns
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HCF4027B
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200K RT = ZOUT of pulse generator (typically 50)
WAVEFORM : PROPAGATION DELAY TIMES, MINIMUM PULSE WIDTH (CK), SETUP AND HOLD TIME (J or K to CK) (f=1MHz; 50% duty cycle)
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HCF4027B
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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HCF4027B
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13H
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HCF4027B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com
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